[Abstract: Part 1: The first part of the talk will address the design, technology, and reliability challenges in pGaN gate-based e-mode HEMT technology and the technological achievements made by my group in IISc. In the second part of this talk, I will talk about a significant positive shift in the threshold voltage by integrating high-k AlxTi1-xO based p-type oxide in AlGaN/GaN HEMT gate stack and how it enabled 600V e-mode GaN HEMTs with superior gate control over channel and ON-state performance. In the third part of the talk, I will discuss the physics of dynamic On-resistance in AlGaN/GaN HEMTs and how the same can be suppressed using p-type AlTiO-based passivation. In the end, I will briefly touch base on some of the other key reliability physics contributions. Part 2 (will try to cover as much as possible within the time left): Dynamic On-resistance (Ron) is a significant reliability concern in Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs), particularly in carbon-doped GaN on Silicon. Several research groups have proposed various models to explain this phenomenon, but many of them were incomplete in their explanations. Some attribute it to surface conditions, while others point to the buffer layer. Previous research often missed to provide a conclusive understanding of the underlying physical mechanism. Furthermore, no solution to address the problem without compromising transistor performance or breakdown voltage has been presented. We have conducted a comprehensive investigation into the dynamic Ron issue, elucidating the interactions between the buffer layer, surface conditions, temperature/self-heating, hot carrier effects, and steady-state versus dynamic stress. We explored different device stacks under various stress scenarios. In this presentation, I will provide insights into the underlying physics and explain how we resolved the issue for 600V-class HEMT devices.](https://www.semix.iitb.ac.in/semix/talk/easing-the-technological-reliability-challenges-of-pgan-gate-based-e-mode-aigan-gan-hemts-by-p-type-aitio-based-gate-stack-and-passivation-engineering/)

Co-sponsored by: SemiX Office

Speaker(s): Prof. Mayank Shrivastava

Room: EEG301, Bldg: GG Vuilding, Seminar Room EEG 301, IIT Bombay, Mumbai, Maharashtra, India