A one day workshop on Verilog HDL with workshop objectives Fundamentals of digital design,Verilog syntax and different modelling styles, and simulation and synthesis.

Room: S-42, Bldg: NIT RAIPUR,MAIN BUILDING, NIT RAIPUR,GE ROAD,AMANAKA,RAIPUR(CG), Raipur, Madhya Pradesh, India, 492010