About the Speaker: “Rodger E. Ziemer received the BSEE, MSEE, and Ph.D. degrees from the University of Minnesota in 1960, 1962, and 1965, respectively. After serving in the U.S. Air Force from 1965-1968, he joined the University of Missouri – Rolla in 1968 where he stayed until 1983, having been promoted through the ranks to Professor. He moved to the Electrical and Computer Engineering (ECE) Department of the University of Colorado at Colorado Springs in January 1984 where he served as Professor and Chairman of ECE until 1993 and then as Professor from September 1993 to the present. In August 1998, he went on leave to the National Science Foundation, where he continues to serve as Program Director for Communications Research. He has spent intermittent periods on leave or sabbatical to various universities and industrial concerns. His principal area of research interest is digital communications. He has authored and co-authored several well-known textbooks in the area of digital communications and applied probability. “
Abstract : The fundamental theory of code-division multiple-access (CDMA) communication systems will be presented, including an overview of spreading codes and their properties, an overview of direct-sequence spread-spectrum communication systems, and application to CDMA as applied to wireless communications. The application of CDMA to second-generation wireless systems will be reviewed, and third-generation wireless standards will be overviewed. Some speculation will be given on what fourth-generation systems will look like with this session ending with an open discussion period.
Individual Participant fees: IEEE members Rs 1200 Non IEEE members Rs 1500 Students Rs 500
Register for the Tutorial by sending in name, e-mail id and address of participants to following e-mail addresses. Fee to be sent as a local cheque drawn in favour of “IEEE Bombay Section” on receipt of confirmation of registration.
Dr. Abhay Karandikar firstname.lastname@example.org
Ashok Jagatia email@example.com
Abstract: Information Technology (IT) is expected to greatly improve the quality of our life by making our society very efficient. It should be noted that the progress of IT entirely owes to that of semiconductor technology, especially, to that of silicon. Silicon integrated circuits provide us high speed/frequency operation of tremendously many functions with low cost, low power, small size, small weight, and high reliability. Progress of silicon integrated circuit has been driven by the downsizing of its components such as MOSFETs. In this talk, downsizing for silicon device technology is explained from the past to future. Especially downsizing into sub-100 nm is presented in detail. Finally, further challenge into sub-10 nm regime is mentioned.
About the Speaker: Prof. Hiroshi Iwai is one of the leading experts on CMOS technology in the world. After graduating from Tokyo University, he spent more than 25 years with Toshiba Corporation, working on important developments on MOSFET physics, CMOS technology, oxide scaling, and RF CMOS. Prof. Iwai’s group at Toshiba demonstrated the first sub-50 nm MOSFET technologies in the early 1990’s. Since 1999, Prof. Iwai has been a Professor at the Tokyo Institute of Technology. Professor Iwai is a Fellow of the IEEE, and a Distinguished Lecturer of the IEEE. His numerous awards include the Grand Prize of Nikkei BP Technology Awards (1994), the IEEE Paul Rappaport Award (1994), and the IEEE J.J. Ebers Award (2001) for “outstanding technical contributions to electron devices”.
ABSTRACT VLSI design methodology is being extended to cover newer areas such as networking applications, special processors, and sytem-on-chip etc. Various steps in the VLSI design procedure will be explained. Simple examples of digital logic and sequential circuits will be given. The trends and the advancement in some of the application areas will be presented. New designs with added features lead to increased complexity, power dissipation, and constraints on speed requirements. Some of the options and related tradeoffs to meet these requirements will be discussed.
ABSTRACT There is considerable interest in understanding and emulating electronically the human brain-mind system due to the possible applications in medical treatment (such as of epilepsy) and in robotics etc. On the lines of development of AI systems, there is an effort to develop electronic systems with Artificial Consciousness (AC). Though the term may not be well-defined, it can encomapss a wide variety of capabilities such as awareness about existing capabilities (in sensing and their interpretation based on past experience), about objectives and choice of best approach to achieve it, about conflict detection and resoultion etc.
The talk will cover the basic building block – the electronic equivalent of biological neuron, the behaviour of neuron assemblies in response to external stimuli and internal signals. Attempts to design micochips to resemble performance of biological system will be presented. The internal system is to be designed so as to respond to the external inputs and environment as well as to get modified to record (store) the changes in the previous states. The next response to the external stimuli is affected by the modified internal system. Some of the models to achieve these will be presented. Self-awareness arising out of self-reference in the internal neural assemblies may lead to realisation of higher levels of consciousness as in the brain-mind complex. Some of the characteristic fearures of the human complex and the aspects which can be possibly be modelled will be discussed.
The planet Earth is moving into multinational companies, strategic alliances, and markets for resource utilization that see no geographical barriers. These international collaborations are creating a dire need for renaissance professionals-skillful and ingenious masters of engineering, economics, and human motivation-those who have vision beyond the confines of their disciplines, organizations or nations. This workshop considers this shift in paradigm and presents heuristics to revive the entrepreneurial spirit by synthesis of ideas from engineering and behavioral sciences, thereby capitalizing on and contributing to the creativity of India’s elites. Creativity is busting the conventional mental blocks and playing with imagination and possibilities, leading to new and meaningful connections and outcomes while interacting with ideas, people and the environment. New paradigms to engineer the direction of the organization you work for, will work for or create one for others to work for are suggested. The attendees will learn to dive for knowledge in the information pool and learn to swim to create a product, procedure or plan that will be of value to the community one lives in, no matter where in the world.
A review of steady-state electronic transport in a high electric field is given. In particular, expressions for mobility and diffusion-coefficient degradation are obtained in the framework of asymmetric distribution function . The concept of a hot electron and its temperature in a given context is discussed and simple analytical expressions extracted. These contextual definitions include: energy temperature, mobility temperature, Einstein-relation temperature both under ac and dc conditions, quantum temperature, and two-band intrinsic temperature. The dependence on the electric field is given in each case and the role of electric-field-induced quantum emission is delineated.  Arora, V. K., Microelectronic Journal, Quantum Engineering of Nanoelectronic Devices: The Role of Quantum Emission in Limiting Drift Velocity and Diffusion Coefficient, 31 853(2000).
The legislated stringent requirement of energy savings in every walk of life demands more efficient power systems. In response, power semiconductor manufacturers world-wide are focussing on the development of high performance power semiconductor devices and ICs. The world market for power semiconductors has grown from $4.94 billion in 1996 to $11 billion in 2001 and is expected to increase with a CAGR of 10% over the next few years. Power semiconductor devices belong to a separate segment of the semiconductor market, differing both in production technology and end-user applications. The power semiconductor industry, in contrast to the low voltage integrated circuit sector with its handful of major mass producers, has still room for smaller industries with innovative, differentiated products. This is because, 70-80% of the power semiconductors are sold directly from the manufacturer to the end user and distribution networks account for the rest. The net successful outcome is set to result in more competitive, highly reliable, and more energy efficient power electronics equipment. Development of innovative, highly differentiated products through smaller power semiconductor manufacturing industries will increase their market share and improve the profitability of the electronics industry. The major driving force for advancing power microelectronics is to achieve cleaner environment through efficient power systems; more efficient use of sustainable resources and added value; and, improve the overall quality of life. In Electric vehicles using fuel cell or hybrid approach, a more efficient inverter is essential and the developments will improve the inverter performance significantly. The photovoltaic systems can also benefit from inverters that are more efficient. The increased reliability of the products can increase the safety aspects of the traction systems. The performance gains will directly reflect in efficiency improvements in automotive, computers, office equipment, consumer electronics, industrial, military & aerospace, communications and consumer white-goods manufacturers, to name a few.
This talk will cover the market issues and advances in power microelectronics, which spans Discrete, Intellgient Power Chips and Power Integrated Circuits. Recent progresses in Diodes, Super Junction Devices, IGBTs to new concepts such as the Clustered IGBT will be covered. Technology advancements such as the Non-Punch-through technology and Field Stop technologies will be highlighted.
The demand for Industry/Academic co-ordinated efforts to advance power microelectronics in India will be identified, which will form the basis for an open discussion.
About the Speaker: Prof. Shankar N Ekkanath Madathil is currently employed as a Research Manager in the Emerging Technologies Research Centre, De Montfort University. He has many years of experience in the field of solid state microelectronics. He has published more than 100 papers within this broad area and has several patent applications pending approval in the area of semiconductor devices. The devices proposed have been cited in textbooks and leading journals.
Prior to joining DMU, he was elected to work as a Maudslay Engineering Research Fellow at Pembroke College, Cambridge (1991-1994) and a Research Associate at the Cambridge University Engineering Department (1993-1994). He joined Cambridge University as a Ph.D. student from India under the prestigious Nehru scholarship in 1987. As a Ph.D. student, he worked to initiate the pioneering research in the area of high voltage integrated circuits within the UK community. The HV-CMOS process developed by him is currently used in Fuji Electronic, Japan and in the UK. In 1994, he was elected to a Senior Stokes Fellowship in Pembroke College.
The Emerging Technologies Research Centre, which he set-up in 1995 within a ‘New University’ has now grown significantly within a short span of time. This Centre has been strategically positioned to attract funding from both industries and academic grant awarding agencies. The research culture of the Centre is based on team-work & quality at international level. Prof. Ekkanath has been acting as a consultant to UK based semiconductor industries. More recently, he has been awarded in excess of £2.5 Million pounds by EPSRC and industries for rapid commercialisation of advanced power devices through strategic alliances with major, international power semiconductor industries based in the USA, UK and other countries. He is a Senior Member of the IEEE and a member of AMBA for the last four years. He is a sub-committee member of the IEEE-ECTC conference in the area of components & RF. He has been awarded the premier BBV Foundation Award from Spain to spend some time as a Visiting Professor at CNM, Spain during the year 2000. More recently, he has been invited to serve as a selection committee member of the EU funded Microserv program, which is part of the EC-Human Potential Access to Research Infrastructure Action program. He has been invited to be part of the International program committee of the IEEE & IEE Co-sponsored International Symposium of Power Semiconductors in Prague, IEEE Co-sponsored International Conference on Microelectronics in Nis, Yugoslavia.
The reason for his visit to India is to identify and seek potential collaborative partners to advance power microelectronics in India.
Self-organization in Nature is a fundamental paradigm that can serve well the thrust towards realization of arrays of semiconductor quantum nanostructure s that are unlikely to be obtained through the conventional paradigm of carving on ever finer length scales. In this talk I shall touch upon some of the emerging self-assembly approaches to nanostructure synthesis and focus on surface stress driven assembly of semiconductor quantum dots and their potential for Optoelectronic (laser, photodtectors, etc.) Electronic (few and single electron) devices.
About the Speaker: Professor Anupam Madhukar Kenneth T. Norris Professor of Engineering Professor of Materials Science and Physics Director, Center for Intelligent Manufacturing of Semiconductors (CIMOS) Member, Laboratory for Molecular Robotics (LMR) Dr. Madhukar received his BSc (1966) and MSc (Physics, 1968) degrees respectively, from the University of Lucknow and the Indian Institute of Technology (Kanpur) in India. He received his Ph.D. in Materials Science and Physics in 1971 from the California Institute of Technology. Before coming to USC in 1976, Dr. Madhukar was a Post Doctoral Research Fellow at the Thomas J. Watson Research Center of the IBM Corporation and a Research Associate at the James Frank Institute of the University of Chicago. Dr. Madhukar was an Alfred P. Sloan Fellow (1977-81), received three NASA Certificates of Recognition (1981, 1982, 1986) for his research in Si/SiO2 interfaces and compound semiconductor MBE, Outstanding Research Award of the USC School of Engineering in 1988, and the DARPA (ETO) award for Sustained Excellence, 1997 (given to a multidisciplinary team lead by Dr. Madhukar). He is the founding President of the Southern California chapter of the Materials Research Society and a member of the New York Academy of Sciences.
Device failure mechanism study is very important in understanding and enhancing the reliability irrespective of the technology limitations. Building in Reliability in devices starts with the design and strengthen through process and testing. The most important aspects of the failure mechanism study are the fail site identification and physical analysis, which becomes a challenge as the technology advances to deep sub-micron regime. The trends in the physical analysis studies to understand the reliability degradations in the latest technology involving ultra thin gate oxides (25-30A) are discussed in this talk. The physical analysis of soft breakdown in these ultra thin gate oxides have been demonstrated to correlate with the electrical failure characteristics. Eventhough reviews on the physical models of thin gate oxide reliability are available, establishing failure mechanisms by physical analysis of device structures is complex and difficult. The direct observation of the breakdown failure mechanism for functional devices is discussed and illustrated using transmission electron microscopic analysis. Effect of stressing on barrier layers as well as gate structure is explained with the physical analysis results. Specific analytical methods such as Focused Ion Beam and Transmission Electron Microscopy used for such physical analysis are explained in view of their significance in establishing the mechanisms to understand the reliability concerns.
Abstract of lecture on :”Design Technology and Architectural Adaptation for Deep Sub-micron VLSI Systems”
We present an assessment of the technology trends and its implications for the computer systems architecture and design tools for the coming generations of process technologies. Based on technology projections from the SIA road-map, the cumulative effect of continuing increases in interconnect delay relative to gate switching would fundamentally alter the ground rules in the design of high performance circuit blocks and the role of interconnect between the circuit blocks. For instance, multiple storage elements could be located in a cycle period whereas block-level interconnect would no longer be a part of the cycle time. Architecturally, increased local decision making can be used to adapt a data-path to application-specific computational requirements. To illustrate how this adaptability can be used in efficient system architectures, we present highlights from the study of latency-hiding mechanisms to improve the interaction of processing and memory elements as a part of the on-going DARPA-sponsored project on high-performance data-intensive embedded computing. From a design technology standpoint, language-level modeling and system co-design of hardware/software blocks under strict timing constraints present a special challenge to the next generation of system design tools. The new design technology must balance increasing technology dependence while advancing the level of abstraction towards target applications. I will present an overview of our work system-level CAD algorithms and describe how system design problems are addressed in a framework that allows the system architect to interactively explore intelligent design options without leaving the application development environment. This talk describes on-going research activity. We welcome participation and feedback from the audience.
SONET has played an important role in the design and operation of a number of networks around the globe. However, it is fast approaching its limits. SONET was originally built for transporting 64-kbps voice channel traffic. It is not exactly suited for the efficient transport of Internet related data traffic. In addition, bandwidth scaling difficulties, quick provisioning and the need for service differentiation necessitates the need to leverage traditional SONET/SDH to newer technologies. We will examine some of the issues that need to considered in the evolution of SONET/SDH to newer network technologies that uses wavelength-division multiplexing-based optical networking technology. We will address issue related to traffic grooming to support IP over WDM, satisfy demands for different Quality of Service (QoS), and survivability issues in WDM-based networks.
The five-layer asymmetric coupled quantum well (FACQW) is expected to show very large electrorefractive index change in a wideband transparency region far from the absorption edge. In an early stage of the study, a Mach-Zehnder interferometer traveling-wave type modulator with the FACQW obtained the modulation bandwidth of 55GHz and the switching voltage of 3 V. In order to realize ultrafast, ultralow voltage, and wideband optical modulators, improvement in growth of the FACQWs is being pursued. In addition, the migration enhanced epitaxy method is being tried for a better heterointerface flatness and a reduced growth temperature.
The ultimate downsizing of the minimum feature size is hampered by physical, technological and economical limitations. To ensure Moore’s law below 100 nm technology nodes both front- and back-end processing has to face technological challenges as clearly stipulated by the International Technology Roadmap for Semiconductors (ITRS). Lithography, gate stack, shallow junctions, high- and low-k dielectrics and interconnect schemes are nowadays amongst the hot research issues leading to a global collaboration. This presentation reviews some of the on-going research efforts to come to cost-effective solutions forming the backbone for future technology generations. The link between micro- and nano-electronics is also addressed.
BIOGRAPHY OF SPEAKER: Cor Claeys was born in Antwerp, Belgium. He received the electrical engineering degree in 1974 and the Ph.D. degree in 1979, both from the Katholieke Universiteit Leuven (KU Leuven), Belgium. His doctoral research was in the field of process-induced defect characterization for VLSI technologies. >From 1974 to 1984 he was, respectively, Research Assistant and Staff Member of the ESAT Laboratory of the KU Leuven and is, since 1990, Professor. In 1984, he joined IMEC, Leuven, as Head of the Silicon Processing Group. Since 1992, he has been responsible for technology business development. His main interests are in general silicon technology for ULSI, device physics including low-temperature operation, low frequency noise phenomena and radiation effects, and defect engineering and material characterization. He co-edited a book on Low Temperature Electronics and has authored and co-authored six book chapters and more than 400 technical papers and conference contributions related to the above fields. Dr. Claeys is a member of the Electrochemical Society, SEMI, the European Material Research Society and a Senior member of IEEE. He is an associate editor for the Journal of the Electrochemical Society. Within IEEE he is presently elected AdCom member of the Electron Devices Society, Chair of the IEEE Benelux Section, Chair of the Benelux ED Chapter and coordinator for ED Chapters in Region 8. In 1999 he has been elected as Academician and Professor of the International Information Academy.
Venue: Fr.C.Rodrigues Institute of Technology, Vashi, New Bombay
Activity of AP/ED Chapter of Bombay Section and IETE
Throughout the past four decades, both the productivity and performance of microelectronics have advanced at exponential rates unmatched in technological history. The number of transistors per microchip has skyrocketed by a factor of about 100 million, while the cost of a chip has remained virtually constant. And the amount of energy consumed in a binary switching transition has been reduced by more than five decades! Consequently, microelectronics has become the principal driver of the modern Information Revolution. And the ubiquitous microchip has had a profound and pervasive impact on our daily life. The current minimum dimension on chip can be as small as as 0.1 micrometers in width, or 1/1,000th the width of a human hair. What made this Microelectronics revolution possible, how is it all done, what lies ahead, and what kind of systems will be prevailing in the year 2010? This Workshop on Microelectronics, being conducted by the Microelectronics group, IIT Bombay will address some of the above questions, and is an excellent opportunity to know more about this field. Microelectronics group at IIT Bombay is one of the most active groups in the country and some of the contributions from this group are recognized the world over. This is an excellent opportunity to interact with them and know more about this field.
For more information, please contact Mr. K. T. V. Reddy firstname.lastname@example.org
During the process of designing high-performance VLSI circuits, designers often find that their silicon implementations do not meet the timing and/or area constraints. Post-layout verification tools have been in use for some time to solve this problem. The basis of these tools is modelling of inteconnect structures. It appears that various physical effects arising out of VDSM technology need to be modeled accurately to predict the circuit element behaviour. One such effect is roughness on interconnects and other circuit elements. ECAE division at IHPC is working on post-layout tools for some time. Recently we have also started work on surface roughness modeling. The talk will also cover our research projects in the area of Test on Chip and Chip Planning Tool for SOC design environment
Biography of the Speaker:
Dr. Ashok Jhunjhunwala is Professor and Head of the Department of Electrical Engineering at IIT Madras. Dr.Jhunjhunwala leads the team that developed corDECT, India’s indigenous Wireless Local Loop technology that’s winning accolades the world over. His research interests span Telecommunications, Computer Networks and Fibre Optics, and he’s particularly active in developing cost-effective wireless telecommunications solutions. The Wireless Local Loop system developed in his lab today is being deployed in Argentina, Brazil, Tunisia, Madagascar, Kenya, Angola, Nigeria, Yemen, Fiji and Iran besides India. The corDECT Wireless in Local Loop provides 35/70 Kbps Internet and simultaneous voice conversation at a cost much lower than that of any other WLL product. Digital Internet Access Switches (DIAS) is a DSL on copper product providing 144 Kbps or 2 Mbps Internet plus simultaneous voice. optiMA Fibre in the Loop system provides SDH fibre back-haul and lowest cost telephony The current mission that Dr.Ashok Jhunjhunwala leads is to enable every village of India to have telecom and Internet connections. Recognising that Internet is power, Dr.Jhunjhunwala and his colleagues have helped formation of the operators company n-Logue Communications Pvt. Ltd., focussed on providing telephone and Internet in every village. The work to provide such connections is going in Madurai and Cuddalore District of Tamil Nadu, Dhar district of Madhya Pradesh and Sikar district of Rajasthan. The objective is to provide 1 million connections in Indian small towns and rural areas in the next three to three and a half years. Dr. Jhunjhunwala is a fellow of INAE, INSA. Indian National Academy of Science, and Governor of International Council for Computer Communications. He is on the Board of Directors of several companies, including Sasken Communications Ltd., Bangalore, Banyan Networks Pvt. Ltd., Chennai, Polaris Software Lab Ltd., Chennai, and n-Logue Communicatons Pvt. Ltd., Chennai. Dr. Jhunjhunwala has received many awards and accolades, among them: 1st Prof.S.N.Mitra Memorial Award, IETE, Dr.Vikram Sarabhai Research Award for the year 1997 towards the contributions and achievements in the field of Electronics, Informatics, Telematics & Automation, the Shanti Swarup Bhatnagar Award for outstanding contributions in the field of Engineering Sciences for the year 1998. And the Distinguished Alumnus award by IIT Kanpur.
One of the greatest challenges facing the scientific and technical communities of the world is to meet the expectations of humanity and contribute to global development in a sustainable manner in the context of burgeoning global population with increasing expectations. Energy is a key player in facing this challenge, Harnessing locally available renewable energy resources to “energize” rural areas, if properly planned and executed, is the most logical approach from both environmental and economic points of view. IRES provide the key to this approach. IRES utilize two or more renewable energy sources and end-use technologies to supply a variety of energy and other needs. It has multiple inputs in different forms and quality. It also has multiple outputs in different forms and quality. Designing IRES involves finding the ratings of the energy conversion and energy storage devices required to satisfy a variety of energy and other needs utilizing locally available renewable energy resources. This seminar will discuss the design considerations and design tradeoffs involved and a knowledge-based approach to the design of IRES.
Biography of Speaker: Dr. Ramakumar received his B.E. from the University of Madras, M.Tech. from IIT- Kharagpur, and Ph.D. from Cornell University, Ithaca, New York. He was associated with the faculty of Coimbatore Institute of Technology for 10 years before joining the Electrical Engineering faculty at Oklahoma State University in Stillwater, Oklahoma, USA. At present he is serving as the PSO/Albrecht Naeter Professor and Director of the Engineering Energy Laboratory. His research interests are in conventional and unconventional energy conversion, power engineering, energy storage, renewable energy, and engineering reliability. His work has been documented in more than 150 publications, including four US patents. He was elected Fellow of IEEE in 1994 for his contributions to renewable energy systems and leadership in power engineering education. Dr. Ramakumar’s textbook entitled Engineering Reliability: Fundamentals and Applications, published by Prentice Hall in 1993 and its Asian edition have been adopted by more than a dozen universities in the US and by several universities around the world. He is the Chairman of the Energy Development Subcommittee and Chairman of the Working Group on Renewable Energy Technologies of the IEEE Power Engineering Society. In addition, he Chairs the Awards Committee of the Technical Council and participates as a member in several other Working Groups, Committees, and Subcommittees of the Power Engineering Society. He is a member of the American and International Solar Energy Societies, American Society for Engineering Education, and is a Professional Engineer in the State of Oklahoma.
Ear type systems are ones which mimic the behavior of biological ears with iour emphasis upon vlsi realization. The systems under discussion use auto-emissions, often called Kemp Echoes, as noninvasive signals from which various 2-port and 4-port lattice models of the inner ear are developed to characterize the inner ear, in some cases through the transfer scattering matrix. From the resulting models vlsi circuits are obtained with various transistorized realizations available including CMOS switched current ones.
Biography of Speaker: Professor Robert W. Newcomb is a Professor at the University of Maryland, and a Life Fellow of the IEEE. He had his education at Purdue (BSEE), Stanford (MS) and Berkeley (Ph.D.). He was on the faculty at stanford University, and, since then, has been at the University of Maryland for more than 25 years, where he is Director of the Microsystems Laboratory. His wide research interests include analog VLSI, biomedical engineering, circuit and systems theory, microsystems, neural networks and robotics. Besides a large number of papers, he is the author of several books, including the well-known classic, “Linear Multiport Sysnthesis”. He is the recipient of the Golden Jubilee Medal and the Education Award of the IEEE CAS Society. He is a Distinguished Lecturer of the IEEE CAS Society. He has been a Visiting Professor in Australia, Malaysia, Spain, Singapore and Korea.
Temporal measurements of sensor arrays are used to estimate signal information in the presence of noise. I will first briefly survey my recent contributions to this area, including electromagnetic and acoustic vector-sensor processing, chemical sensor array processing, biomedical applications, and antenna arrays for communications. I will then focus on the case of electro- and magneto-encephalography (E/MEG) sensor arrays for detecting electric sources in the brain. These arrays measure electric potentials on the scalp and magnetic fields around the head. I will present maximum likelihood methods for estimating evoked responses, which allow for spatially correlated noise between sensors with unknown covariance. The electric sources will be modeled as current dipoles. I will estimate the unknown dipoles’ locations and moments, and present Cramer-Rao lower bounds on their estimation errors. Numerical examples will be shown to illustrate the results for real data, including the accuracy to which sources can be localized in different regions in the brain.
Arye Nehorai received the B.Sc. and M.Sc. degrees in electrical engineering from the Technion-Israel Institute of Technology, in 1976 and 1979 respectively, and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, in 1983. After graduation he worked as a Research Engineer for Systems Control Technology, Inc., in Palo Alto, CA. From 1985 to 1995 he was with the Department of Electrical Engineering at Yale University, New Haven, CT, where he became an Associate Professor in 1989. In 1995 he joined the Department of Electrical Engineering and Computer Science at The University of Illinois at Chicago (UIC), as a Full Professor. He is currently Chair of the department’s Electrical and Computer Engineering Division and is managing the creation of a new ECE Department at UIC. He holds a joint professorship with the Bio-engineering Department at UIC. His research interests are in signal processing, communications, and biomedicine. Dr. Nehorai is Editor-in-Chief of the IEEE Transactions on Signal Processing. He is also a Member of the Publications Board of the IEEE Signal Processing Society and the Editorial Board of Signal Processing. He has previously been an Associate Editor of the IEEE Transactions on Acoustics, Speech and Signal Processing, of IEEE Signal Processing Letters, the IEEE Transactions on Antennas and Propagation, the IEEE Journal of Oceanic Engineering, and Circuits, Systems, and Signal Processing. He served as Chairman of the Connecticut IEEE Signal Processing Chapter from 1986 to 1995 and is currently the Chair and a Founding Member of the IEEE Signal Processing Society’s Technical Committee on Sensor Array and Multichannel (SAM) Processing. He was the co-General Chair of the First IEEE SAM Signal Processing Workshop, held in 2000, and will serve in this position in 2002. He was co-recipient, with P. Stoica, of the 1989 IEEE Signal Processing Society’s Senior Award for Best Paper. He received the Faculty Research Award from UIC College of Engineering in 1999. He has been a Fellow of the IEEE since 1994 and of the Royal Statistical Society since 1996.
Dr. Abhijeet V. Chavan is a Design Manager with Delphi Automotive Systems, affiliated with there Delco Electronics Division. He obtained his PhD from the University of Michigan, Ann Arbor. His primary area of development/research is silicon based MEMS and related CMOS/BiCMOS interface techniques. In the presentation scheduled for July 11 Dr. Chavan will present MEMS development by discussing two specific silicon MEMS devices namely, an Absolute Capacitive Pressure sensor and an Infra-Red Sensor. Important issues in design, simulation, process, test and system integration for such devices will be discussed.
This is a story about a Silicon Valley startup with a twist. There is no successful or unsuccessful endpoint to report. This is simply a view from the middle – from someone who is there now and going through it. How do companies get started, how are great investors, VCs and employees brought in, how is the product developed, how are customers won, how is value created,what are the challenges being faced? How will the story end? We dont know, time will tell.
A high voltage transformer is subjected to transient over voltages due to lightning and switching surges. The insulation provided to withstand the power frequency highest system voltage is often found inadequate due to non uniform voltage distribution across the transformer winding specially under lightning impulse. The degree of non uniformity depends on the ratio of equivalent shunt and series capacitance. The search for a suitable design led to the development of interleaved winding. The efficiency of a design can be tested on a model using analogue and digital techniques. The digital simulation of a 31.5 MVA , 132 kV Transformer shows that interleaving can reduce the degree of non uniformity to a large extent in the main winding but the regulating winding suffers from part winding resonance which may lead to break down of insulation. The part winding resonance can be damped to a great extent by the use of graded interleaving technique. The testing technique involves detection of fault under rated impulse voltage and its location. Fault identification can be done by visual investigation of current oscillograms or by digital techniques. Frequency Spectrum Analysis is a reliable tool in fault diagnosis. Use of ANN and Neuro Fuzzy techniques helps in the location of fault. However, a generalised technique in the location of fault in all types of winding is yet to be evolved.
– Silicon Pressure sensors
– MicroElectroMechanical Systems
MICROFABRICATION AND MICROMACHINING
– Integrated Circuit Processes
– Bulk Micromachining
* Isotropic Etching
* Anisotropic Etching
– High Aspect-Ratio Processes (LIGA)
– Classification of physical sensors
– Integrated, Intelligent, or Smart sensors
– Sensor Principles and Examples
* Thermal sensors
* Electrical Sensors
* Mechanical Sensors
CHEMICAL AND BIOMEDICAL SENSORS
– Chemical and Biosensors
– Electromagnetic and Thermal microactuation
– Mechanical design of microactuators
– Microactuator examples
– Microactuator systems : Success Stories
* Ink-Jet printer heads
* Micro-mirror TV Projector (opposite of CCD camera chip)
– One or two sacrificial layer processes
– Surface micromachining requirements
– Polysilicon surface micromachining
– Other compatible materials
* Silicon Dioxide
* Silicon Nitride
* Piezoelectric materials
– Surface Micromachined Systems : Success Stories
* Gear trains
PACKAGING AND TESTING TECHNIQUES
– Assembly and Packaging
Challenges / Responsibilities:
– Develop proprietary MEMS fabrication processes
– Design processes compatible with device requirements
– Transfer fabrication processes from prototype to volume production
– Maintain baselines for existing processes
– Process troubleshooting
– All-mechanical miniature devices
– 3-D electromagnetic actuators and sensors
– Photonic devices
– Medical devices e.g. DNA-chip, micro-arrays
Abstract: In the CMOS-MEMS process a standard CMOS process is used for fabrication of MicroElectroMechanical Systems (MEMS). This talk presents the multi-domain modeling efforts required to simulate a CMOS-MEMS gyroscope. Following a brief introduction to the microgyroscope, elastic and electrostatic models needed to capture non-idealities in the gyroscope will be described. Ongoing work on a SPICE-like simulation methodology based on a hierarchy of design levels (similar to that existing in the digital VLSI world) will be outlined. A synthesis tool aimed at automated layout generation from high-level functional specifications of the gyroscope is also being developed on the basis of the simulation framework. This work is being done in collaboration with other researchers at the Carnegie Mellon MEMS Laboratory.
Narain Arora, Ph.D., is Vice President, Technology at Simplex Solutions, Inc. Prior to joining Simplex in 1996 he held several engineering and management positions within DEC’s semiconductor division over a 14-year period. The most recent being consulting engineer and manager of DEC’s device and interconnect modeling group. His field of interest is semiconductor process/device design and modeling/characterization including VLSI device/circuit reliability and parasitic (interconnect) modeling and extraction. He has given various invited talks and published over 45 Journal papers and authored a book “MOSFET Modeling for VLSI Circuit Simulation: Theory and Practice”, Springer-Verlag, NY 1993.
Abstract: As CMOS technology shrinks to Ultra deep sub-micron geometries (below 0.18um), the propagation delay due to interconnects (wiring) begins to dominate the total chip delay. In fact, parasitic due to interconnects are becoming limiting factors in determining circuit performance. An accurate modeling of the interconnects parasitic effects is thus essential in determining various interconnect related issues such as delay (timing), cross-talk, IR drop, power dissipation, electromigration, etc. This talk will cover different approaches available in modeling the interconnects and what are the challenges the chip designers and CAD vendors are facing to solve the problem.
Abstract:We discuss the recent advances in oxide ferroelectric thin films and their integration into both high-density DRAMs and non-volatile memories (FRAMs). Emphasis will be placed on integration aspects of these thin films, breakdown mechanisms and limits, leakage currents, electrodes and electrode interfaces, scaling to submicron geometries, and deposition techniques.
Slate given by Nominations Committee
RSVP Letter of acknowledgement
Theme… “Software Challenges Ahead”
Abstract: This lecture will explore the development of the Demand-side Management (DSM) concept and answer questions like — what is DSM, why DSM, how DSM can be used for energy and capacity savings, and how transmission and distribution credits can be obtained from DSM. The talk will also examine the financial viability (in terms of customer acceptance) and the future of DSM in the age of electric utility restructuring. Various energy efficiency programs being offered by energy service companies and US electric utilities will be discussed. The value of energy efficiency in dealing with the global climate change issues will be investigated. The present times of electrical power shortages have to be handled diligently & efficiently. Maharashtra Electricity Regulatory Commission has made a start by offering reduced rates during lean periods (Rs.0.50 rebate per unit during 10.00 AM to 6.00 PM for HT consumers.) & enhanced rates during peak hours (Rs.0.30 extra charge for units consumed during 9.00 AM to 12.00 Noon & Rs.0.60 extra per unit during 6.00 PM to 10.00 PM) The DSM has become a wide science with many interesting facets.
Abstract: The talk draws from the current experience at Intel, Bangalore of designing such multi-million gate ASICs. It starts with what happens at Project kickoff in defining the ASIC as a part of a System solution for market requirements, how technology selection is done, how chip complexity and chip /board cost is estimated, and how development resources and schedule are estimated. The body of the talk is on the sequential front end steps in designing the ASIC – Architecture, micro-architecture, usage of IP cores, RTL, Design for test, validation, floorplan, synthesis, timing analysis – using examples from real-life multi-million gate ASICs being designed in the industry. The talk also touches on Project management aspects, and waterfall vs spiral model for development. Finally comments are made about what key issues must be driven in order to make a project of this size and complexity achieve first silicon success.
Seminar by Dr. Lucky Vishnubhotla International SeMaTech, Austin, TX 78741, USA
Venue:EE Seminar Hall, IIT Bombay
“Key Challenges in Gate Module for Deep Submicron CMOS Technologies”
Lecture by Dr. Narain Hingorani -US based consultant and earlier VP of Electrical systems at EPRI, USA.
“Power Electronics for Power Quality / Customer Power”
Venue:MSEB Hall, Prakashgad, MSEB Head-Quarters, Bandra (E)
Lecture by Mr. S. V. Deo, Technical Member, MSEB
“The Perspectives of Maharashtra State Electricity Board”
Venue:Institutions of Engineers, Pune
Arranged jointly with PES/IAS Bombay Chapter & Institutions of Engineers, Pune
Lecture by Lov K. Grover, Bell Labs, Murray Hill, USA
Venue:EE Seminar Hall, IIT Bombay
Lecture by Avshalom C. Elitzur, Visiting Professor, Bhaktivedanta Institute, Juhu, Mumbai. Faculty, Bar Ilan University, Israel. Consultant, Weizmann Institute of Science, Israel
“Year 2000 IEEE Bombay Section Student Paper and Project Contest”
“Inaugration of AP/EDS Joint Chapter”
Venue:EE Seminar Hall, IIT Bombay
Slate given by Nominations Committee
RSVP Letter of acknowledgement
Minutes of AGM held on 20th Mar 99
Programme of IEEE TAB Colloquia in Mumbai
“Artificial Neural Networks: Principles and Applications ”
(For Faculty, Professionals, Engineers,Scientists, etc.)
Slate given by Nominations Committee
RSVP Letter of acknowledgement
Lecture by Dr T R N Rao
“Cryptology, A Modern Science, for Computer Age”
” Two day Tutorial-cum-Workshop on Image Processing”
Lecture by Dr T R N Rao
“Computing Science, in Ancient India”
” One day Seminar on Global Mobile Personal Communication System (GMPCS)”
“Income Tax Planning for Salaried Technical Professional” by S.N. Katdare\
Lecture by Dr R Sengupta
“Surface Mount Technology”
Lecture by Prof Michele Poloujadoff
“Economic Appraisal of Losses in Electrical Machinery:Principle,Evolution”
“Codes for Detection and Correction of Errors in Computer”
Lecture by Dr S V Palkar
“Internet and its Demonstration”
Prof V M Gadre and others
“1½ day workshop on Digital Signal Processing”