IEEE Bombay EDS Chapter : Schottky Barrier Height Engineering for Low Resistance Contacts to Semiconductor Devices by Prof. Krishna Saraswat

Title:  Schottky Barrier Height Engineering for Low Resistance Contacts to Semiconductor Devices

Speaker:  Prof. Krishna Saraswat
Rickey/Nielsen Chair Professor of Electrical Engineering, Stanford University

Date and Time:  Monday, December 30, 2013 — 11:30 am

Place:  GG Conference Room, 3rd Floor Girish Gaitonde Building, IIT Bombay


The scaling of conventional bulk silicon CMOS faces several obstacles necessitating the need to introduce materials such as germanium and III-Vs together with novel structures such as FinFET. As device scaling continues, parasitic source resistance largely dominated by contact resistance, becomes a limiting factor to the on current. Specific contact resistivity ρc of a metal-semiconductor (M/S) contact is dependent on the Schottky barrier height phi_B, and the electrically active dopant density N at that interface. In M/S contacts the metal Fermi level is pinned at the charge neutrality level ECNLresulting in fixed electron and hole Schottky barrier heights phi_BN and phi_BP. High values of phi_BN and phi_BP and low value of N results in high ρc, eclipsing the promise of intrinsic performance of MOSFETs and other devices. To obtain low ρc it is essential to reduce phi_BN and phi_BP and increase N.
Fermi level pinning occurs because wave functions of electrons in the metal tail can decay into the semiconductor in the band gap, creating metal-induced gap states (MIGS). The charge neutrality level (ECNL) is the energy level at which the interface states change from donor like to acceptor  like.Charging of these states by the metal wavefunction creates a dipole charge causing the Fermi level to align to minimize the dipole charge towards zero, effectively pulling the EF at the interface towards ECNL.

Historically the method to reduce ρc is by increasing Nto > 5E19/cm3 thereby thinning the barrier, thus allowing more tunneling current. This method works well for n and p type Si and p-Ge which can be doped heavily. However, it is not very practical for n-Ge, most III-Vs and 2D materials because of inability to dope them heavily.Second method is to create an additional dipole at the M-S interface to modulate the barrier height by incorporating a dopant or chalcogens close to the interface to modulate the dipole. This dipole modulates the barrier height.Third method is by inserting a thin dielectric between the metal and semiconductor with the aim of depinning the Schottky barrier height. The ultrathin insulatorallows the metal electron wavefunction to be attenuated in the insulator prior to penetrating the semiconductor resulting in fewer MIGS thus depinning the Fermi level. The metal workfunction can then be used to tune the effective barrier height. This method has been used to obtain low phi_B and thus lowρc in Si, Ge and III-V semiconductors. This method will be described in detail in this talk.

Speaker Bio:

Krishna Saraswat received Ph.D. in Electrical Engineering from Stanford University in 1974.  He is Rickey/Nielsen Chair Professor in the School of Engineering, Professor of Electrical Engineering and by courtesy Professor of Materials Science & Engineering at Stanford University. His research interests are in new and innovative materials, structures, and process technology of silicon, germanium and III-V devices and interconnects for VLSI, nanoelectronics and solar cells. Areas of his current interest are: new device structures to continue scaling MOS transistors and DRAMs to nanometer regime, 3-dimentional ICs with multiple layers of heterogeneous devices, ultrathin MOS gate dielectrics, metal and optical interconnections, and high efficiency and low cost solar cells. He has graduated more than 80 doctoral students and has authored or co-authored over 700 technical papers, of which 10 have won best paper award. He is a Life Fellow of the IEEE. He received the Thomas Callinan Award from The Electrochemical Society in 2000 for his contributions to the dielectric science and technology, the 2004 IEEE Andrew Grove Award for seminal contributions to silicon process technology, Inventor Recognition Award from MARCO/FCRP in 2007, the Technovisionary Award from the India Semiconductor Association in 2007 and the SIA Researcher of the Year Award in 2012. He is listed by ISI as one of the 250 Highly Cited Authors in his field.

© 2018 IEEE Bombay Section | All Rights Reserved | WebSite Designed by IEEE Bombay Section